SynaptiCAD TestBencher Pro

Free yourself from the time-consuming process of writing Verilog and VHDL test benches by hand. Generate them graphically from timing diagrams using SynaptiCAD's WaveFormer Pro, VeriLogger Pro, or TestBencher Pro software packages.

TestBencher Pro is a VHDL, Verilog, OpenVera, e, and TestBuilder Graphical Test Bench generator that dramatically reduces the time required to create and maintain test benches.

TestBencher Pro is a graphical test bench generator that dramatically reduces the time required to create and maintain test benches.
One of the most time consuming tasks for users of HDL languages is coding test benches to verify the operation of their design.

TestBencher Pro automates the most tedious aspects of test bench development, allowing you to focus on the design and operation of the test bench. This is accomplished by representing each bus transaction graphically and then automatically generating the code for each transaction.

TestBencher Pro makes use of the powerful features of the language that is being generated and the engineer does not have to hand-code each transaction. When hand coding, the designer would have to take the time to deal with the specifics of the design (port information, monitoring system response, etc) as well as common programming errors (race conditions, minor logic errors, and code design problems). This removes a considerable amount of time from the test bench design process because TestBencher manages the low-level details and automatically generates a valid test bench.

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